1. Field of the Invention
The present invention relates to a computer system comprising a plurality of computers interconnected by a network and, more particularly, to a computer system wherein many computers transfer packets to each other via local and global networks.
2. Description of the Related Art
Now, referring to FIG. 2, there is shown a conventional computer network in which a plurality of nodes 201 (node #1, node #2, . . . node #N) are linked to each other via a network 202. Each of the plurality of nodes 201 includes an instruction processor (IP) 203, a local memory (LM) 204, a transmit circuit (TX) 205, and a receive circuit (RX) 206 which are linked to each other via an address bus and a data bus 207. Referring to FIG. 3, there is shown the format of a data packet 301 for use in the network illustrated in FIG. 2. The packet 301 includes a preamble 302 containing a fixed bit pattern, a destination node address 303, a source node address 304, a packet type 305, a data field 306 fetched from the local memory 204 of a send node, and CRC (Cyclic Redundancy Checksum) 307. The data packet 301 is sent to the network by the transmit circuit (TX) 205 and received from the network by the receive circuit (RX) 206.
In what follows, the conventional art is described with reference to FIGS. 2 and 3.
In order to transfer the data packet 301 via the network 202, the instruction processor 203 of the send node forms an image of data to be sent in an output buffer in the local memory 204. Then, the instruction processor 203 issues a send command to the transmit circuit 205, the command includes information such as the address and packet type of the destination node, the location of the output buffer in the local memory 204, and the length of data field.
Receiving the send command, the transmit circuit 205 sets an in-transmission flag, fetches the data field from the output buffer in the local memory 204, and starts sending the data packet 301. When the send command has been completed, the transmit circuit 205 resets the in-transmission flag and outputs an interrupt request to the instruction processor 203 via an interrupt request signal line 208.
Meanwhile, the receive circuit 206 monitors the network 202. Detecting the packet 301, the receive circuit 206 synchronizes its circuit with the incoming data stream by using the preamble 302 and then receives the destination node address 303. Then, if this address matches an address unique to the receive node itself, the receive circuit 206 receives all the remaining portions of the packet.
The CRC is recalculated to check if the packet 301 has been received correctly. The result of the recalculation is compared with the CRC 307 at the end of the packet. The result of the comparison is used to generate a receive status flag for the packet. The send node address, packet type, data field length, receive status flag and data field thus received are stored in the input buffer in the local memory 204 of the receive node. Then, an interrupt request is issued to the instruction processor 203 via the interrupt request signal line 208.
In a conventional computer network system, a send node has no means for controlling, directly by hardware, an interrupt request or a status flag in a receive node. Hence, if the instruction processor in the receive node is waiting for a particular packet or the last packet in a packet group to be received, the instruction processor must wait for an interrupt request to be caused for each packet and, when the interrupt request has been caused, check the receive status flag to see if the received packet matches the requested packet by using packet type and the data field information, thereby determining whether the desired packet has been received or not. If a packet other than the desired one has come, the instruction processor must wait for a next interrupt. Consequently, an interrupt request made at receiving other than the desired packet imposes a heavy load on the processor in the receive node. That is, the unnecessary interrupt service and the check for a match between the received packet and the desired packet are a waste of time for the instruction processor.
Further, in the conventional computer network system, hardware control of a queue or chain of send commands for sending a plurality of packets is not provided, hence control of such a queue or chain requires instruction processor operation. Consequently, if one node must transmit a plurality of packets consecutively, the instruction processor must wait for an interrupt to be caused at the end of the packet transmission by the current send command before issuing the next send command. Servicing the interrupt wastes the instruction processors time. The transmit circuit in an idle state while the interrupt is being serviced, thereby is also wasting the transmit circuits time.